1. Field of the Invention
The present invention relates to a clamp pulse generating circuit and more particularly to a circuit for generating clamp pulses used for keeping a pedestal level of a brightness signal in a video signal at constant level.
2. Description of the Related Art
Because DC component is lost in a capacitive coupling amplifier circuit and colors of color images cannot be reproduced faithfully in a video signal processing circuit, pedestal clamp in which a pedestal level of a brightness signal is clamped by clamp pulses to keep it at constant level is carried out to reproduce the DC component lost by the capacitive coupling. A circuit for generating the clamp pulses used for the pedestal clamp has been adapted to generate the pulses in a timing slightly behind a horizontal synchronizing pulse at that in general.
In a pedestal clamp circuit using the clamp pulse generating circuit constructed as described above, the pedestal level has been clamped at a back porch 6 in a horizontal blanking period 2 of a video signal 1 shown in FIG. 1, because the clamp pulse is generated in the timing behind the horizontal synchronizing pulse. However, in the field of computer displays and the like, horizontal frequency tends to be increased with the increase of the resolution and because the gap of the back porch portion 6 becomes narrow as the horizontal frequency is increased, a pulse width of the clamp pulse has to be narrowed.
Then, a problem that a power consumption increases occurs when the pulse width of the clamp pulse is set narrower because an output impedance at an output stage has to be lowered so as not to blunt the waveform of the clamp pulse in the clamp pulse generating circuit. When the blunted waveform of the clamp pulse was input to the pedestal clamp circuit on the other hand, it posed a problem that a situation in which an accurate pedestal level cannot be held or in the worst case, the pedestal clamp cannot be performed may occur.
Accordingly, it is an object, of the present invention to provide a clamp pulse generating circuit which can generate a clamp pulse having a desired pulse width in generating the clamp pulse at an external synchronizing pulse.